Application of Generalized Power-Delay Metrics to Supply and Threshold Selection in Deep Submicron CMOS

Application of Generalized Power Delay Metrics to Supply and Threshold Selection in Deep Submicron CMOS by Dipanjan Sengupta Power consumption has become as important as performance in todays deep submicron designs. As a result, high-level techniques and models must be developed to evaluate design changes in terms of power (energy) and performance tradeoff early in the design process. Recently, designers have been using the energy-delay product as a metric of goodness for CMOS designs due to certain perceived shortcomings of the more traditional power-delay product. As the industry moves to 90nm technology and encountered higher leakage currents, it is appropriate to revisit existing design metrics. In this thesis, a more general view of power and delay metrics for design optimization has been provided along with how these metrics can be used for design optimization. Supply (V D D) and threshold (VT) voltage scaling are two popular methodologies of power reduction. As such, the effect on power and frequency are analyzed and the feasible region of operation is identified in the V D D vs. V T plane. A fundamental relationship is established between the optimal operating points and the generalized design metrics. In addition, new power and delay models are developed for logic blocks that incorporate the effect of V D D and V T . The effect of optimization on power and delay with respect to process, temperature and voltage variation has also been investigated.